1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a densification and a size reduction (miniaturization) of a complementary MOS transistor.
2. Description of the Background Art
Heretofore, in order to highly densify a transistor, the transistor is made to have a vertical structure, as disclosed in Japanese Patent Laid-Open No. 61-93656 (1986).
There is also a structure wherein a gate electrode of a complementary transistor is buried in a trench formed in a substrate, as disclosed in Japanese Patent Laid-Open No. 62-165356 (1987).
However, a conventional semiconductor device and a method of manufacturing the same have problems of a large number of diffusion layers, and increase in the number of process steps.
Also, since the conventional manufacturing method includes an epitaxial growth step, there is a problem of change in the profile of impurity content due to the thermal history thereof. Therefore, the problem that the process control is difficult arises.
The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful semiconductor device.
A more specific object of the present invention is to facilitate the densification and size reduction of semiconductor devices.
The above object of the present invention is attained by a following semiconductor device.
According to one aspect of the present invention, the semiconductor device comprises a substrate in which a shallow trench having a depth of 0.05 xcexcm to 0.1 xcexcm is formed. A gate insulating film formed on sidewalls and a bottom of the shallow trench, and a surface of the substrate contacting upper ends of the sidewalls. Gate electrodes formed on the both sidewalls of the shallow trench each through the gate insulating film. Impurity diffusion layers formed on the bottom of the shallow trench, and the surface of the substrate contacting the upper ends of the sidewalls of the shallow trench.